1. Field of the Invention
The present invention relates to a variable length decoder decoding code data that is encoded into variable length codes.
2. Description of the Related Art
As a method for compressing and expanding moving picture data, international standards such as MPEG-2 and MPEG-4 are known (See ISO/IEC 14496-10:2003, “Information technology, Coding of audio-visual objects-Parts 10:Advanced video coding”). In recent years, an LSI and a software core based on these international standards are surely installed in the digital consumer electrical appliance dealing with a moving picture.
According to these international standards, moving picture data is divided into a block of 8×8 pixels or into a macro block of 16×16 pixels, and data processing is performed in a block unit or a macro block unit.
Encoders for compressing moving picture data such as MPEG2 and MPEG4 comprise mainly a discrete cosine transformer (DCT), a quantizer (Q), and a variable length encoder (VLC). Inputted pixel data is first transformed into frequency domain data from space domain data by the discrete cosine transformer. When the pixel data consists of a natural scene image and is transformed into the frequency domain data, the data concentrates in a low frequency domain.
Next, among the frequency domain data obtained by the discrete cosine transformer, quantizing is roughly performed in a quantizer in order to make a coefficient of a high frequency component take the value “0”. Then, among the frequency data, non-zero coefficients are concentrated in low frequency components and all the data in high frequency component is transformed into the value “0”. In the variable length encoder, a data set of non-zero and zero is generated performing a zigzag scan so that the data is composed in an order from the low frequency components to the high frequency components, that is, the value “0” may be easily gathered. This data set is encoded into variable length codes using a table of the Huffman code to obtain variable length encoded data.
The above-mentioned variable length encoded data is provided through a recording medium or a network. A decoder for decoding moving picture data by decoding the variable length encoded data generally comprises a variable length decoder (VLD), an inverse quantizer (IQ), and an inverse discrete cosine transformer (IDCT).
FIG. 15 is a block diagram illustrating the conventional image decoding device. The conventional image decoding device illustrated in FIG. 15 comprises an encoded data memory 1, and a variable length decoder (VLD) 2, which includes an address generator 2a, a coefficient data memory 3, an inverse quantizer (IQ) 4, and an inverse DCT 5. The encoded data memory 1 stores variable length encoded data in which moving picture data is encoded into variable length codes. The coefficient data memory 3 stores a run-length value that is coefficient data (that is, quantized data) transformed by the variable length decoder 2.
An outline of operation of the conventional image decoding device illustrated in FIG. 15 is explained in the following.
When variable length encoded data is provided to the variable length decoder 2 from the encoded data memory 1, the variable length decoder 2 initializes the coefficient data memory 3. That is, the variable length decoder 2 performs a clear processing as this initialization processing by writing in a value “0” to all the addresses of the coefficient data memory 3.
A processing of image data in an image decoding device is generally performed in a macro block unit. For example, when the structure ratio of pixel data is Y: Cb: Cr=4:2:0, one macro block comprises Y: 16×16 pixels, Cb: 8×8 pixel, and Cr: 8×8 pixels which is a total of 384 pixels. Therefore, initialization for 384 symbols is required for initialization of one macro block. (One pixel usually has a pixel value of one symbol consisting of 8 bits.) When an initialization processing of one cycle per pixel is required, 384 cycles are required for the initialization processing of one macro block.
After the initialization processing is completed, the variable length decoder 2 checks variable length encoded data (bit string) from the encoded data memory 1 with the variable length decoding table which is prepared independently, and decodes the variable length encoded data to quantized data. Among the quantized data, only thenon-zero quantized data is written in the coefficient data memory 3. An address generator 2a generates an address where the non-zero quantized data should be written in the coefficient data memory 3.
Thereby, when decoding processing for one macro block is completed, decoding processing for the next macro block is performed. Here, in order to perform decoding processing for a new macro block in the conventional image decoding device illustrated in FIG. 15, the coefficient data memory 3 needs to be initialized. Since every decoding processing for macro blocks needs this initialization, the ratio of time required for initialization processing results in a lot of time being wasted in the decoding.
In the conventional image decoding device illustrated in FIG. 15, the number of decoding cycles which is required until the last coefficient data (quantized data) is stored is as follows.(decoding cycles)=(at least 384 cycles of initialization processing)+(the number of symbols of non-zero)*(the number of decoding cycles per symbol in VLD)
The number of one symbol is equivalent to one quantized data.
Since a low operation frequency is desirable in the image decoding device installed in a portable device powered by a battery, it is also desirable for the above-mentioned decoding cycle to be low in operation frequency cycle. However, in recent years, the number of decoding cycles is increasing because of an increase in screen size and in the number of moving picture processing frames in a unit time, therefore the cycle numbers required for initialization processing need to be small. Furthermore, every decoding processing of a macro block requires 384 cycles of access for the initialization processing of the coefficient data memory 3, so power consumption tends to increase. The number of access times to the coefficient data memory 3 needs to be reduced.
FIG. 16 is a block diagram that is improved so that the time required for an initialization processing is reduced compared to the conventional image decoding device as in FIG. 15. That is, FIG. 16 is the block diagram of the improved conventional image decoding device. In FIG. 16, explanation is omitted by giving the same symbols regarding the same components as in FIG. 15.
As illustrated in FIG. 16, the improved conventional image decoding device comprises a coefficient data memory 3a and a coefficient data memory 3b that are installed in parallel, and a converter 6 which converts the coefficient data memory 3a and the coefficient data memory 3b one after the other.
In the improved conventional image decoding device illustrated in FIG. 16, when variable length encoded data is provided from the encoded data memory 1 to the variable length decoder 2, the variable length decoder 2 first initializes the coefficient data memory 3a. After initialization is completed, the variable length decoder 2 converts selection of the converter 6, and initializes the coefficient data memory 3b. Simultaneously, the variable length decoder 2 checks the variable length encoded data (bit stream) from the coded data memory 1 with the variable length decoding table which is prepared independently, decodes quantized data, and writes only the non-zero quantized data among the quantized data in the coefficient data memory 3a. 
Thus, the effect of the time required in initialization processing is reduced by converting the two coefficient data memory 3a and 3b that are installed in parallel, and by performing the initialization processing and decoding processing and data writing processing in parallel.
In the improved conventional image decoding device illustrated in FIG. 16, the number of decoding cycles which is required until the last coefficient data (quantized data) is stored is the greater of (at least 384 cycles of initialization processing) and (the symbol numbers of non-zero)*(the number of decoding cycles per symbol in the VLD). However, the two coefficient data memory 3a and 3b need to be installed in the improved conventional image decoding device illustrated in FIG. 16, therefore increase in a circuit area can not be avoided.